Highly Resistive Substrate CMOS on SOI

Highly Resistive Substrate CMOS on SOI for Wireless Front-End Applications (Invited Paper) Randy Wolf1, Dawn Wang2, Alvin Joseph1, Peter Rabbeni2, Alan Botula1, and Jim Dunn1 1 IBM, 1000 River St, Essex Junction, VT 05452, USA 2 IBM, 5 Technology Park Dr, Westford, MA 01886, USA Email: rwolf@us.ibm.com
This paper describes 0.18 um CMOS silicon-on-insulator (SOI) technology, modeling, and design techniques for SOI RF switches for wireless applications. The measured results for SP8T (single pole eight throw) and SP12T (single pole twelve throw) switch reference designs are presented. It has been demonstrated that SOI RF switch power handling, linearity, insertion loss, and isolation is very competitive with those parameters of switches using GaAs pHEMT and silicon-on-sapphire (SOS) technologies, while maintaining a cost and manufacturing advantage. LNA (low noise amplifier) and power cells for PA cores are also presented to demonstrate the integration possibilities.

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This paper describes 0.18 um CMOS silicon-on-insulator (SOI) technology, modeling, and design techniques for SOI RF switches for wireless applications. The measured results for SP8T (single pole eight throw) and SP12T (single pole twelve throw) switch reference designs are presented. It has been demonstrated that SOI RF switch power handling, linearity, insertion loss, and isolation is very competitive with those parameters of switches using GaAs pHEMT and silicon-on-sapphire (SOS) technologies, while maintaining a cost and manufacturing advantage. LNA (low noise amplifier) and power cells for PA cores are also presented to demonstrate the integration possibilities.