0.1mm InP HEMT MMIC Fabrication on 100 mm Wafers for Low Cost, High Performance Millimeter-Wave Applications

J Uyeda, R. Grundbacher, R. Lai, D. Umemoto, P.-H. Liu, M. Barsky, A. Cavus, L.J. Lee, J. Chen, J. Gonzalez, S. Chen, R. Elmadjian, T. Block, and A. Oki

Northrop Grumman Space Technology, Redondo Beach, CA 90278

Tel: (310) 813-4329, Fax: (310) 813-3301, Email: Jensen.Uyeda@ngc.com

 

Keywords: Indium Phosphide, High Electron Mobility Transistor, Monolithic Microwave Integrated Circuit

 

Abstract

Northrop Grumman Space Technology (NGST) has recently initiated process development for fabricating 0.1 mm InGaAs/InAlAs/InP High Electron Mobility Transistor (HEMT) MMICs on 100 mm InP substrates.  Successful development of this process will further reduce costs of InP HEMP MMICs and rival those of GaAs-based HEMT MMICs, including GaAs-based metamorphic HEMT technology, with superior performance.  Production capability has been demonstrated in three core areas:  expitaxial material growth using Molecular Bean Epitaxy (MBE), frontside processing in NGST’s 100 mm MMIC production line, and backside processing in NGST’s 100 mm backside production line with final wafer thickness of 75 mm.  In this paper, we will present recent data and progress on NGST’s 0.1 mm InP HEMT MMIC LNA process on 100 mm InP substrates.

 

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