Interlayer and Intershot Charging-Induced Pattern Distortion on GaAs Substrates Exposed with a High Throughput Shaped Beam Electron Beam Lithography System

 

A. Bross*, R. Davis*, T. Toyama**, J. Been*

*TriQuint Semiconductor Texas, 500 West Renner Rd. Richardson, TX  75080

abross@tqtx.com, 972-994-5630

**Hitachi Instruments Service, Yotsuya 4-28-8 Shinjuku-ku, Tokyo 160-0004

 

Keywords: Electron beam lithography, charging, t-gate, overlay, pattern distortion, Espacer

 

Abstract

Electron beam lithography is a viable option for exposure of high-resolution patterns such as t-gates in GaAs manufacturing, in part due to the speed and ease of use of modern electron beam direct write tools.  In order to achieve greater speed, these tools utilize higher beam current densities and variable shaped beams.  The resulting higher beam currents at the resist surface, however, can create significant amounts of pattern misplacement due to resist charging effects.  In many cases, the misalignment results in unacceptable layer-to-layer overlay and a lower yielding process.  Understanding the amount of charging, its effects on a process, and how to minimize the effect are keys to maintaining a high-throughput t-gate process.  This paper will present quantitative results of charging effects on semi-insulating, ion implanted, and pHEMT GaAs substrates.  We show that a polymeric anti-charging layer is effective in reducing pattern displacements to an acceptable level, even in the extreme case of the exposure of semi-insulating substrates.

 

3.3 pdf             Return to TOC