Application of IVS Overlay Measurement to Wafer Deformation Characterization Study

Ying Liu and Iain black

ANADIGICS INC., 141 Mt. Bethel Road, Warren, NJ  07059

E-mail: yliu@anadigics.com; jblack@anadigics.com

Tel: (908) 668-5000 x6335m x6139

 

Keywords: IC gallium-arsenide process, Overlay measurement, GaAs wafer thermal distortion, and GaAs wafer deformation

 

Abstract

This work revealed on of the applications of overlay error measurement on investigation of GaAs wafer distortion during the normal high-temperature thermal process (above 800oC), using IVS overlay system.  The results showed good correlation between the IVS overlay measurement and the temperature variation maps of the wafer obtained from temperature graduation experiments and electrical tests.  The overlay error increased with increasing temperature.

 

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