Wafer-Level Reliability Tests of InGaP HBTs Using High Current Stress

 

Frank H.F. Chau, Chien-Ping Lee*, Clarence Dunnrowicz and Barry Lin

EiC Corporation, 45738 Northport Loop West, Fremont, CA 94538, USA

Tel: (510) 979-8943, fax: (510) 979-8901, email: fchau@eiccorp.com

* Permanent Address: Dept. of Electronics Engineering, National Chiao Tung University, 1001 Ta Hsueh, Hsinchu, Taiwan

 

ABSTRACT

 

Current densities ranging from 440 to 543 kA/cm 2 were applied to InGaP HBTs in WLR tests. Even with such a high current stress at 440 kA/cm 2 and an estimated junction temperature of 396 C, the transistor lasted for 101 hours before our failure criterion was met. The current gain degradation behavior was similar to that shown in traditional, low current reliability tests, namely a long, relatively stable or slow gradual degradation region after the initial stabilization took place, followed by a sudden, rapid gain degradation phase that led to device failure. The failure, however, was characterized by 1kT current increase in the base current, in contrast to the 2kT current increase at a much lower current density of 50 kA/cm 2 in traditional reliability tests. A mixed failure mode was observed at 75 kA/cm 2 stress current density. It is believed that biasing HBTs much beyond base pushout regime results in defect generation deep in the base through REDR associated with increased neutral base recombination. It is further supported by the fact that the lifetime of transistor appears to depend more on the applied base current, and not so much on the collector current density and junction temperature. WLR tests at extremely high current densities cannot replace traditional low current stress tests to predict HBT lifetime under the normal use conditions.

 

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