Reduction of Average Cycle Time at a Wafer Fabrication Facility

Reduction of Average Cycle Time at a Wafer Fabrication Facility
Subhash C. Sarin and Sameer T. Shikalgar
Grado Department of Industrial and Systems Engineering This paper is concerned with the development of effective solutions for the reduction of average cycle time at a wafer fabrication facility. The wafer fabrication environment is quite different from the usual flow shop or job shop environments, with a distinguishing feature being the reentrant flow of the lots through the system. Lots at different stages of their manufacturing cycle may revisit the machines. This gives rise to the need of effective policies to sequence lots through the system.

Two methodologies have been developed to effect a reduction in the cycle time. The first methodology is a heuristic procedure based on the idea of reducing idle time on the bottleneck machine. The second methodology is based on mathematical programming.

The proposed methodologies are implemented using the data obtained from the M/A-COM's wafer fabrication facility in Roanoke, Virginia. The facility consists of ninety-two machines and its products can be classified into six different types. The performance of one of the proposed methodologies is compared with that of the policies currently followed at the M/A-COM facility in Roanoke, Virginia and the results are presented.